1. Field of the Invention
The present invention relates to a 1-bit signal processor comprising an nth order Delta-Sigma Modulator having a filter section where n is at least one. Preferred embodiments of the invention relate to processing audio signals but the invention is not limited to audio signal processors.
2. Description of the Prior Art
Background to the present invention will now be described by way of example with reference to FIGS. 1, 2 and 3 of the accompanying drawings of which FIG. 1 is a block diagram of a known Delta-Sigma Modulator, FIG. 2 is a block diagram of a previously proposed Delta-Sigma Modulator configured as an 3rd order (n=3) filter section and FIG. 3 shows a noise shaping characteristic.
It is known to convert an analogue signal to a digital form by sampling the analogue signal at at least the Nyquist rate and encoding the amplitudes of the samples by an m bit number. Thus if m=8, the sample is said to be quantized to an accuracy of 8 bits. In general m can be any number of bits equal to or greater than 1.
For the purpose of quantizing to only 1 bit, it is known to provide an analogue to digital converter (ADC) known either as a "Sigma-Delta ADC" or as a "Delta-Sigma ADC". Herein the term "Delta-Sigma" is used. Such an ADC is described in for example "A Simple Approach to Digital Signal Processing" by Craig Marven and Gillian Ewers ISBN 0-904.047-00-8 published 1993 by Texas Instruments.
Referring to FIG. 1 in an example of such an ADC, the difference 1 (Delta) between an analogue input signal and the integral 2 (Sigma) of the 1-bit output signal is fed to a 1-bit quantizer 3. The output signal comprises bits of logical value 0 and 1 but representing actual values of -1 and +1 respectively. The integrator 3 accumulates the 1-bit outputs so that value stored in it tends to follow the value of the analog signal. The quantizer 3 increases (+1) or reduces (-1) the accumulated value by 1-bit as each bit is produced. The ADC requires a very high sampling rate to allow the production of an output bit stream the accumulated value of which follows the analogue signal.
The term "1-bit" signal as used in the following description and in the claims means a signal quantized to an accuracy of 1 digital bit such as is produced by a Delta-Sigma ADC.
A Delta-Sigma Modulator (DSM) configured as nth order filter section for directly processing a 1-bit signal was proposed by N. M. Casey and James A. S. Angus in a paper presented at the 95th AES Convention Oct. 7-10, 1993 New York, USA entitled "One Bit Digital Processing of Audio Signals"--Signal Processing: Audio Research Group, The Electronics Department, The University of York, Heslington, York YO1 5DD England. FIG. 2 shows a 3rd order (n=3) version of such a DSM filter section.
Referring to FIG. 2, the DSM has an input 4 for a 1-bit audio signal and an output 5 at which a processed 1-bit signal is produced. The bits of the 1-bit signal are clocked through the DSM by known clocking arrangements which are not shown. The output 1-bit signal is produced by a 1-bit quantizer Q which is for example a comparator having a threshold level of zero. The DSM has three stages each comprising a first 1-bit multiplier a.sub.1, a.sub.2, a.sub.3 connected to the input 4, a second 1-bit multiplier c.sub.1, c.sub.2, c.sub.3 connected to the output 5, an adder 6.sub.1, 6.sub.2, 6.sub.3 and an integrator 7.sub.1, 7.sub.2, 7.sub.3. Each integrator has a delay of 1 bit period.
The 1-bit multipliers multiply the received 1-bit signal by p bit coefficients A.sub.1, A.sub.2, A.sub.3, C.sub.1 C.sub.2, C.sub.3 producing p bit products which are added by the adders 6.sub.1, 6.sub.2, 6.sub.3 and the sums passed to the integrators 7. In the intermediate stages the adders 6.sub.2, 6.sub.3 also sum the output of the integrator of the preceding stage. A final stage comprises another 1-bit multiplier A.sub.4 connected to the input which multiplies the input signal by a p bit coefficient A.sub.4 and an adder 6.sub.4 which adds the product to the output of the integrator 7.sub.3 of the preceding stage. The sum is passed to the quantizer 2.
Within the DSM, two's complement arithmetic may be used to represent the positive and negative p bit numbers. The input to the quantizer Q may be positive, quantized at the output as +1 (logical 1) or negative quantized at the output as -1 (logical 0).
As observed by Casey and Angus "a one bit processor . . . will produce a one bit output that contains an audio signal that is obscured by noise to an unacceptable level and it is imperative the quantization noise is suitably shaped". The noise which obscures the audio signal is the quantization noise produced by the quantizer Q.
The quantizer Q may be modelled as an adder which has a first input receiving an audio signal and a second input receiving a random bit stream (the quantization noise) substantially uncorrelated with the audio signal. Modelled on that basis, the audio signal received at the input 4 is fed forward by multipliers a.sub.1, a.sub.2, a.sub.3, a.sub.4 to the output 5 and fed back by multipliers c.sub.1, c.sub.2, c.sub.3 from the output 5. Thus coefficients A1 to A4 in the feed forward path define zeros of the Z-transform transfer function of the audio signal and coefficients C1-C3 in the feed back path define poles of the transfer function of the audio signal.
The noise signal, however is fed-back from the quantizer by the multipliers C.sub.1 -C.sub.3 so that coefficients C.sub.1 -C.sub.3 define poles of the transfer function of the noise signal. The transfer function of the noise signal is not the same as that of the input signal.
The coefficients A1 to A4 and C1 to C3 are chosen to provide circuit stability amongst other desired properties.
The coefficients C1-C3 are chosen to provide noise shaping so as to minimise quantization noise in the audio band, as shown for example in FIG. 3 by the full line 31.
The coefficients A1-A4 and C1-C3 are also chosen for a desired audio signal processing characteristic.
The coefficients A1-A4 and C1-C3 may be chosen by:
a) finding the Z-transform H(z) of the desired filter characteristic--e.g noise shaping function; and PA1 b) transforming H(z) to coefficients. PA1 a first combiner for forming an integral of an additive combination of the product of the input signal and a first coefficient and of the product of the output signal and a second coefficient, PA1 at least one intermediate combiner each for forming an integral of an additive combination of the product of the input signal and a first coefficient and of the product of the output signal and a second coefficient, and of the integral of the preceding stage, and a final combiner for forming an additive combination of the product of the input signal and a first coefficient and of the integral of the preceding stage to form the said p bit signal which is requantized by the quantizer to form the 1-bit output signal, wherein PA1 the said input signal is fed to the first combiners of the first and intermediate combiners via a delay corresponding to the delay through a combiner, and to the final combiner without such delay, the 1-bit output signal of the quantizer is fed-back to the combiners via an equal delay and the final combiner receives from its preceding combiner a p-bit signal corresponding in timing to the input signal received by the final combiner.
This may be done by the methods described in the papers "Theory and Practical Implementation of a Fifth Order Sigma-Delta A/D Converter, Journal of Audio Engineering Society, Volume 39, no. 7/8, 1991 July/August by R. W Adams et al."and in the paper by Angus and Casey mentioned hereinbefore and using the knowledge of those skilled in the art. One way of calculating the coefficients is outlined in the accompanying Annex.
The DSM is clocked at the sampling rate of the 1-bit signal. For audio this rate may be in the range about 2.8 kHz to about 2.8 MHz, preferably 2.8224 MHz. {character pullout} DSM of FIG. 2 has a final adder 64 coupled to the first adder 61 via only the quantizer Q and the feedback path. All the other adders are coupled via integrator stages 71,72,73 each of which has a delay of one bit period. In an implementation in which the adders 61,62,63 take at least a major portion of a bit period in which to produce a settled sum the adders 64 and 61 slow the operation of the circuit.